11.30

Refreshments and Networking

12.00

Introduction, Mike Bartley, TVS

12.05

Eric Deal – Cyclic Design

Title:  Using Zocalo's Zazz to Implement Assertions in the Design/Verification Process

Abstract:  Assertions are a powerful tool that both design and verification engineers can use to shorten verification debug time and quickly identify failures within a design.  While the large processor companies rely heavily on assertions, few design teams in other areas have adopted them.   This presentation discusses the benefits of using SystemVerilog Assertions (SVA), barriers to SVA adoption and how Zocalo's Zazz has enabled Cyclic Design to easily and effectively implement assertions in its IP, benefiting both internal verification as well as customer integration.

Bio

Eric is the founder and President of Cyclic Design, a silicon IP/consulting company specializing in error correction solutions for NAND flash.  He has 18 years digital logic design and architecture experience developing ASICs and SOCs with expertise in error correction (ECC), encryption, security, image processing, system bus, clocking, and I/O interfaces.  Eric promoted the use of OVL assertions while at Conexant and was an early adopter of SystemVerilog assertions while at Sigmatel.  He has a Bachelor's Degree in Electrical Engineering from Texas A&M University.

12.45

Nitin Mhaske – NextOp Software

Title:  Assertion Synthesis Case Studies

Abstract:  Assertion synthesis is a technology that automatically generates functional assertions and coverage properties based on simulation testbench and RTL. In this talk, we will present several case studies of assertion synthesis, focusing on how the technology has been used in production verification flows.  Real life bug stories will be shared.

Bio:  Nitin is Member of Technical Staff at NextOp and handles deployment of assertion synthesis technology for clients across various industry segments and verification methodologies. He has over 11 years of industry experience and has lead block/chip level verification activity at leading semiconductor companies in past. He has a bachelor’s degree from Pune University, India.

13.20

Closing Q & A

13.30

Refreshments and Networking

14.00

Finish